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[AK4121A]
AK4121A
Asynchronous Sample Rate Converter
GENERAL DESCRIPTION The AK4121A is a stereo asynchronous sample rate converter. The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. Since the internal PLL eliminates the need for a master clock in slave mode, the AK4121 simplifies the system design. Therefore, the AK4121A is suitable for applications requiring multiple sample rates, such as Car Audio, DVD recorders, and digital audio recording.
FEATURES Stereo asynchronous sample rate converter Input sample rate range (FSI): 8kHz to 96kHz Output sample rate (FSO): 32kHz/44.1kHz/48kHz/96kHz Input to output Sample rate ratio: FSO/FSI = 0.33 to 6 THD+N: -113dB I/F format: MSB justified, LSB justified (24/20/16bit) and I2S Clock for Master mode: 256/384/512/768fso De-emphasis filter: 32kHz/44.1kHz/48kHz SRC Bypass mode Soft Mute function Power Supply: VDD: 3.0 to 3.6V, TVDD: 3.0 to 5.5V (for input tolerant) Ta: -40 to +85C
PDN DEM0 DEM1 SMUTE TVDD VDD DVSS
(MCLK) SDTI ILRCK IBICK SDTO OLRCK OBICK
Serial Audio I/F
De-em filter
Sample Rate Converter
soft mute
Serial Audio I/F
CMODE2 AVSS FILT PLL CMODE1 CMODE0
IDIF2
IDIF1
IDIF0
ODIF1
ODIF0
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[AK4121A]
Ordering Guide
AK4121AVF AKD4121A -40 +85C 24pin VSOP (0.65mm pitch) Evaluation Board for AK4121A
Pin Layout
FILT AVSS PDN SMUTE DEM0 DEM1 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD DVSS TVDD MCLK OLRCK OBICK SDTO ODIF1 ODIF0 CMODE2 CMODE1 CMODE0
Top View
Difference between AK4121 and AK4121A
The AK4121A has a better performance than the AK4121 regarding of the tracking capability to the change of the input sampling frequency (FSI) which normally takes long settling time. Refer to "Tracking to the Input Sampling Frequency".
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[AK4121A]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name FILT AVSS PDN SMUTE DEM0 DEM1 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 CMODE0 CMODE1 CMODE2 ODIF0 ODIF1 SDTO OBICK OLRCK MCLK TVDD DVSS VDD I/O O I I I I I I I I I I I I I I I I O I/O I/O I I I I Function Loop-Filter Pin for PLL Analog Ground Pin Power-Down pin When "L", the AK4121A is powered-down and reset. Soft Mute Pin De-emphasis Filter Control Pin #0 De-emphasis Filter Control Pin #1 L/R Clock Pin for Input Audio Serial Data Clock Pin for Input Audio Serial Data Input Pin Input Data Format pin #0 Input Data Format pin #1 Input Data Format pin #2 Clock Mode Select Pin #0 Clock Mode Select Pin #1 Clock Mode Select Pin #2 Output Data Format pin #0 Output Data Format pin #1 Audio Serial Data Output Pin Audio Serial Data Clock Pin for Output L/R Clock Pin for Output Master Clock Pin for Output Input Buffer Power Supply Pin, 3.3V or 5V Digital Ground Pin Power Supply Pin, 3.3V
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[AK4121A]
ABSOLUTE MAXIMUM RATINGS
(AVSS=DVSS=0V; Note 1) Parameter Core Input Buffer |AVSS-DVSS| (Note 1) Input Current, Any Pin Except Supplies Input Voltage Ambient Temperature (Power applied) Storage Temperature Power Supplies: Symbol VDD TVDD GND IIN VIN Ta Tstg min -0.3 -0.3 -0.3 -40 -65 max 4.6 6.0 0.3 10 TVDD+0.3 85 150 Units V V V mA V C C
Note 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS=DVSS=0V; Note 2) Parameter Power Supplies: Core Input Buffer Note 2. All voltages with respect to ground. Symbol VDD TVDD min 3.0 VDD typ 3.3 5 max 3.6 5.5 Units V V
SRC PERFORMANCE (Ta=-4085C; VDD=3.03.6V; TVDD=3.0~5.5V; data=20bit; measurement bandwidth=20Hz~FSO/2; unless otherwise specified.) Parameter Symbol min typ max Resolution 20 Input Sample Rate FSI 8 96 Output Sample Rate FSO 32 96 Dynamic Range (Input= 1kHz, -60dBFS, Note 3) 114 FSO/FSI=44.1kHz/48kHz 114 FSO/FSI=48kHz/44.1kHz 114 FSO/FSI=32kHz/48kHz 115 FSO/FSI=96kHz/32kHz 112 Worst Case (FSO/FSI=48kHz/96kHz) Dynamic Range (Input= 1kHz, -60dBFS, A-weighted, Note 3) 117 FSO/FSI=44.1kHz/48kHz THD+N (Input= 1kHz, 0dBFS, Note 3) -113 FSO/FSI=44.1kHz/48kHz FSO/FSI=48kHz/44.1kHz -112 FSO/FSI=32kHz/48kHz -113 FSO/FSI=96kHz/32kHz -111 Worst Case (FSO/FSI=48kHz/8kHz) -103 Ratio between Input and Output Sample Rate FSO/FSI 6 (FSO/FSI, Note 4, Note 5) 0.33
Note 3. Measured by Rohde & Schwarz UPD04, Rejection Filter= wide, 8192point FFT. Note 4. The "0.33" is the ratio of FSO/FSI when FSI is 96kHz and FSO is 32kHz Note 5. The "6" is the ratio when FSI is 8kHz and FSO is 48kHz.
Units Bits kHz kHz dB dB dB dB dB dB dB dB dB dB dB -
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[AK4121A]
DIGITAL FILTER (Ta=-4085C; VDD=3.03.6V; TVDD=3.0~5.5V) Parameter Symbol min Digital Filter Passband -0.001dB 0.985 FSO/FSI 6.000 PB 0 0.905 FSO/FSI < 0.985 PB 0 0.714 FSO/FSI < 0.905 PB 0 0.656 FSO/FSI < 0.714 PB 0 0.536 FSO/FSI < 0.656 PB 0 0.492 FSO/FSI < 0.536 PB 0 0.452 FSO/FSI < 0.492 PB 0 0.333 FSO/FSI < 0.452 PB 0 Stopband 0.985 FSO/FSI 6.000 SB 0.5417FSI 0.905 FSO/FSI < 0.985 SB 0.5021FSI 0.714 FSO/FSI < 0.905 SB 0.3965FSI 0.656 FSO/FSI < 0.714 SB 0.3643FSI 0.536 FSO/FSI < 0.656 SB 0.2974FSI 0.492 FSO/FSI < 0.536 SB 0.2732FSI 0.452 FSO/FSI < 0.492 SB 0.2510FSI 0.333 FSO/FSI < 0.452 SB 0.1822FSI Passband Ripple PR Stopband Attenuation SA 96 Group Delay (Note 6) GD -
typ
max 0.4583FSI 0.4167FSI 0.3195FSI 0.2852FSI 0.2245FSI 0.2003FSI 0.1781FSI 0.1092FSI
Units kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB 1/fs
0.01 57.5 -
Note 6. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output, when LRCK for Output data corresponds with LRCK for Input.(at 20bit MSB justified, 16bit and 20bit LSB justified)
DC CHARACTERISTICS (Ta=-4085C; VDD=3.0~3.6V; TVDD=3.0~5.5V) Parameter Symbol min Power Supply Current Normal operation: FSI=FSO=48kHz at Slave Mode: VDD=3.3V FSI=FSO=96kHz at Master Mode: VDD=3.3V : VDD=3.6V Power down: PDN = "L" (Note 7) High-Level Input Voltage VIH 0.7xVDD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-400A) VOH VDD-0.4 VOL Low-Level Output Voltage (Iout=400A) Input Leakage Current Iin Note 7. All digital inputs including clock pins are held DVSS.
typ
max
Units
10 20 10 -
40 100 0.3xVDD 0.4 10
mA mA mA A V V V V A
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[AK4121A]
SWITCHING CHARACTERISTICS (Ta=-4085C; VDD=3.0~3.6V; TVDD=3.0~5.5V; CL=20pF) Parameter Symbol min Master Clock Input (MCLK) Frequency fCLK 8.192 Duty Cycle dCLK 40 L/R clock for Input data (ILRCK) Frequency fs 8 Duty Cycle Duty 48 L/R clock for Output data (OLRCK) Frequency (Note 8) fs 32 Duty Cycle Slave Mode Duty 48 Master Mode Duty Audio Interface Timing Input IBICK Period 1/64fs tBCK IBICK Pulse Width Low 65 tBCKL IBICK Pulse Width High 65 tBCKH ILRCK Edge to IBICK "" (Note 9) ILRCK period (8KHz ~ 32KHz) 1/256fs+45 tBLR ILRCK period (32KHz ~ 48KHz) 1/256fs+25 tBLR ILRCK period (48KHz ~ 96KHz) 1/256fs+15 tBLR 30 tLRB BICK "" to ILRCK Edge (Note 9) 30 tSDH SDTI Hold Time from IBICK "" 30 tSDS SDTI Setup Time to IBICK "" Output (Slave Mode) OBICK Period 1/64fs tBCK OBICK Pulse Width Low 65 tBCKL OBICK Pulse Width High 65 tBCKH OLRCK Edge to OBICK "" (Note 9) 30 tBLR 30 tLRB OBICK "" to OLRCK Edge (Note 9) tLRS OLRCK to SDTO (MSB) tBSD OBICK "" to SDTO Output (Master Mode) BICK Frequency fBCK BICK Duty dBCK tMBLR -20 BICK "" to LRCK tBSD -20 BICK "" to SDTO Power-down & Reset Timing PDN Pulse Width (Note 10) tPD 150
Note 8. Min is 8kHz when BYPASS="H". Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4121A must be reset by bringing PDN pin "H" to "L" upon power-up.
typ -
max 36.864 60 96 52 96 52
Units MHz % kHz % kHz % %
50
50 50
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Hz % ns ns ns
30 30 64fs 50 20 30
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[AK4121A]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Figure 1. Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK
VIH VIL tLRS tBSD 70%VDD 30%VDD tSDS tSDH VIH VIL
SDTO
SDTI
Figure 2. Audio Interface Timing at Slave Mode
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[AK4121A]
LRCK
50%VDD
tMBLR BICK
dBCK 50%VDD
tBSD 50%VDD
SDTO
Figure 3. Audio Interface Timing at Master Mode
tPD VIH VIL
PDN
Figure 4. Power-down & Reset Timing Note 11. BICK means IBICK and OBICK. Note 12. LRCK means ILRCK and OLRCK.
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[AK4121A]
OPERATION OVERVIEW
System Clock
The input port works in slave mode only. The output port works in slave and master mode. An internal system clock is created by the internal PLL using ILRCK. The MCLK is not needed when the output port is in slave mode, and the MCLK pin should be connected to DVSS. The CMODE2-0 pins must be controlled when PDN pin ="L". Mode 0 1 2 3 4 5 6 7 CMODE2 L L L L H H H H CMODE1 L L H H L L H H CMODE0 MCLK L 256fso (fso~96kHz) H 384fso (fso~96kHz) L 512fso (fso~48kHz) H 768fso (fso~48kHz) L Not used. Set to DVSS H L H Not used. Set to DVSS Table 1. Master/Slave control Master/Slave (Output Port) Master Master Master Master Slave (Reserved) (Reserved) Master (BYPASS mode)
Audio Interface Format
The IDIF2-0 pins select the data mode for the input port. The ODIF1-0 pins select the data mode for the output port. In all modes the audio data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of OBICK. Select these modes when PDN pin="L". In BYPASS mode, both IBICK and OBICK are fixed to 64fs. Mode 0 1 2 3 4 IDIF2 L L L L H IDIF1 L L H H L IDIF0 SDTI Format L 16bit LSB Justified H 20bit LSB Justified L 20bit MSB Justified H 20/16bit I2S Compatible L 24bit LSB Justified Table 2. Input Audio Data Formats SDTO Format OBICK (Slave) 16bit LSB Justified 64fs 20bit LSB Justified 64fs 20/16bit MSB Justified 40fs or 32fs 20/16bit I2S Compatible 40fs or 32fs Table 3. Output Audio Data Formats IBICK (Slave) 32fs 40fs 40fs 40fs or 32fs 48fs
Mode 0 1 2 3
ODIF1 L L H H
ODIF0 L H L H
OBICK (Master) 64fs 64fs 64fs 64fs
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[AK4121A]
LRCK
0 1 12 13 14 15 16 31 0 1 12 13 14 15 16 31 0 1
BICK (64fs) SDTI 16bit SDTI 20bit
Don't care 15:MSB, 0:LSB Don't care 19 18 17 16 15 0 Don't care 19 18 17 16 15 0 15 0 Don't care 15 0
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. 16bit/20bit LSB justified Timing
LRCK
0 1 2 18 19 20 30 31 0 1 2 18 19 20 30 31 0 1
BICK (64fs) SDTI
19 18 1 0 Don't care 19 18 1 0 Don't care 19 18
20:MSB, 0:LSB
Lch Data
Figure 6. 20bit MSB justified Timing
Rch Data
LRCK
0 1 2 3 19 20 21 31 0 1 2 3 19 20 21 31 0 1
BICK (64fs) SDTI
19 18 1 0 Don't care 19 18 1 0 Don't care 19
19:MSB, 0:LSB
Lch Data
Figure 7. 20bit I S Timing
2
Rch Data
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[AK4121A]
Soft Mute Operation
When the SMUTE pin changes to "H", the output signal is attenuated from 0dB to -dB during 1024 OLRCK cycles. When the SMUTE pin returns to "L", the attenuation is cancelled and the output signal gradually changes to 0dB during 1024 OLRCK cycles. If the soft mute is cancelled before attenuating to -, the attenuation is discontinued and returns to 0dB by the same cycles. The soft mute is effective for changing the signal source.
SMUTE
0dB Attenuation Level at SDTO
-dB
(1) (1)
(2)
Notes: (1) Transition time. 1024 OLRCK cycles (1024/fso). (2) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to 0dB by the same number of clock cycles. Figure 8. Soft Mute
De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc=50/15s) and is enabled or disabled with DEM0 and DEM1. Mode 0 1 2 3 DEM1 L L H H DEM0 L H L H De-emphasis filter 44.1kHz OFF 48kHz 32kHz
Table 4. De-emphasis Filter Control
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[AK4121A]
System Reset
Bringing the PDN pin="L" places the AK4121A in the power-down mode and initializes the digital filter. This reset should always be done after power-up. When the PDN pin = "L", the SDTO output is "L". Regarding the SDTO valid time, please refer to the Table 5. Until the output data becomes valid, the SDTO pin outputs "L".
Case 1
External clocks (input port) SDTI External clocks (output port) PDN
(1)
don't care don't care don't care
(state1) (state1) (state1)
(state2) (state2) (state2)
don't care don't care don't care
ta tb
normal operation PD PLL lock & fs detection normal operation
(internal state) Power-down SDTO
PLL lock & fs detection
Power-down
"0" data
normal data
"0" data
normal data
"0" data
Case 2
External clocks (input port) SDTI External clocks (output port) PDN
(1)
(no clock) (don't care) (don't care)
(state1) (state1) (state1)
don't care don't care don't care
(internal state) Power-down SDTO
PLL Unlock
PLL lock & fs detection
normal operation
Power-down
"0" data
normal data
"0" data
Note: (1) <100ms for recommended value 2, <200ms for recommended value 1. (Figure 11) Figure 9. System Reset Reset time Data valid time ta tb <100ms 10ms 10ms< <200ms Table 5. Reset time ta and Data valid time tb.
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[AK4121A]
Internal Reset Function for Clock Change
The AK4121A is reset automatically when the output clock is stopped. If the output clock is started again, normal data is output within 100ms.
Sequence of changing clocks
The recommended sequence for changing clocks is shown in Figure 10.
External clocks (input port or output port) PDN
state 1
(unknown)
state 2
< 10msec < 100msec
(interlal state) SDTO
normal operation
Power down (1)
PLL locktime & fs detection
normal operation
normal data
normal data 1024/fso
SMUTE (2) (recommended) Att.Level 0dB -dB
1024/fso
Figure 10. Sequence of changing clocks Note: (1) The data on SDTO may cause a clicking noise. To prevent this, set SDTI to "0" from GD before the PDN pin changes to "L", which will cause the data on SDTO to remain "0". (2) SMUTE can also be used to remove the unknown data.
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[AK4121A]
Grounding and Power Supply Decoupling
The AK4121A requires careful attention to power supply and grounding arrangements. VDD are usually supplied from the system's analog supply. AVSS and DVSS of the AK4121A must be connected to the analog ground plane. System analog ground and digital ground should be connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors especially a 0.1F ceramic capacitor for high frequency noise should be placed as near to VDD as possible.
PLL Loop-Filter
The C1 (4.7F) and R (560ohms) should be connected in series and attached between FILT pin and AVSS in parallel with C2 (1.0nF). A Care should be taken to ensure that noise on the FILT pin is minimized.
AK4121A
FILT R C1
C2
AVSS
Parameter Recommended value 1 Recommended value 2 R 560ohm +/-8% 1.2kohm +/-8% C1 4.7F +/-40% 2.2F +/-40% C2 1.0nF +/-40% 2.2nF +/-40% FSI range 8k ~ 96kHz 16k ~ 96kHz Note 13. Those recommended values include temperature dependence. Figure 11. PLL Loop-Filter
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[AK4121A]
Jitter Tolerance
Figure 12 shows the jitter tolerance to ILRCK. The jitter quantity is defined by the jitter frequency and the jitter amplitude shown in Figure 12. When the jitter amplitude is 0.01UIpp or less, the AK4121A operates normally regardless of the jitter frequency.
AK4121A Jitter Tolerance
10.00
1.00 Amplitude [UIpp]
(3)
0.10
(2)
0.01
(1)
0.00 1 10 100 Jitter Frequency [Hz] 1000 10000
(1) Normal operation (2) There is a possibility that the distortion degrades. (It may degrade up to about -50dB.) (3) There is a possibility that the output data is lost. Note 14. The jitter amplitude for 1UI (Unit Interval) is one cycle of ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8s. Figure 12. Jitter Tolerance
Tracking to the Input Sampling Frequency
When the ILRCK is generated by an external PLL, it may take a time to settle after changing the input sampling frequency because the response of an external PLL to the frequency change is slow. In case of the AK4121, the output data becomes incorrect when the speed of the frequency change exceeds 0.14%/sec. The AK4121A operates normally up to 23%/sec speed and the output data becomes incorrect at the speed of the frequency change over 23%/sec.
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[AK4121A]
SYSTEM DESIGN
Figure 13 and Figure 14 illustrate typical system connection diagrams. The evaluation board [AKD4121A] demonstrates this application circuit, the optimum layout, and power supply arrangement and performance measurement results.
+ 10u 0.1u 4.7u 560 1.0n FILT AVSS PDN SMUTE Control DEM0 DEM1 fsi DSP1 ILRCK IBICK SDTI IDIF0 IDIF1 Mode setting (fix to "H" or "L") IDIF2 VDD 0.1u DVSS TVDD MCLK +3.3~5V Digital (*1) fso DSP2 +3.3V Analog
AK4121A
OLRCK OBICK SDTO ODIF1 ODIF0 CMODE2 CMODE1 CMODE0
Figure 13. Example of a typical design (Slave Mode)
+ 10u 0.1u 4.7u 560 1.0n FILT AVSS PDN SMUTE Control DEM0 DEM1 fsi DSP1 ILRCK IBICK SDTI IDIF0 IDIF1 Mode setting (fix to "H" or "L") IDIF2 VDD 0.1u DVSS TVDD MCLK 256fso fso 64fso DSP2 +3.3~5V Digital (*1) +3.3V Analog
AK4121A
OLRCK OBICK SDTO ODIF1 ODIF0 CMODE2 CMODE1 CMODE0
Figure 14. Example of a typical design (Master Mode; MCLK=256fso) *1. TVDD should be the same as the maximum input voltage.
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[AK4121A]
PACKAGE
24pin VSOP (Unit: mm)
*7.90.2 1.250.2
24
13 *5.60.2 A 7.60.2 0.15
+0.1 -0.05
1 0.220.1
12 0.65
0.10.1 Detail A 0.50.2 0.10 0-10
Epoxy Cu Solder plate (Pb free)
Seating Plane
NOTE: Dimension "*" does not include mold flash.
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
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[AK4121A]
MARKING
AKM AK4121AVF AAXXXX
Contents of AAXXXX AA: Lot# XXXX: Date Code
REVISION HISTORY
Date (YY/MM/DD) 04/09/01 07/06/05 Revision 00 01 Reason First Edition Error Correct Page 4 Contents SRC PERFORMANCE Dynamic Range, Worst Case FSO/FSI=32kHz/44.1kHz 48kHz/96kHz SWITCHING CHARACTERISTICS Audio Interface timing ILRCK Edge to IBICK "" is changed to ILRCK period (8kHz ~ 32kHz): 1/256fs+45 ILRCK period (32kHz ~ 48kHz): 1/256fs+25 ILRCK period (48kHz ~ 96kHz): 1/256fs+15 Internal Reset Function for Clock Change Sequence of Changing Clocks
Description Change Description Change
6
07/07/25
02
13
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[AK4121A]
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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